1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of semiconductor devices, and, more specifically, to various hybrid fin cutting processes for FinFET semiconductor devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially field effect transistors (FETs), are provided and operated on a restricted chip area. FETs come in a variety of different configurations, e.g., planar devices, FinFET devices, nanowire devices, etc. These FET devices are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region.
In contrast to a planar FET, which, as the name implies, is a generally planar structure, a so-called FinFET device has a three-dimensional (3D) structure. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 that will be referenced so as to explain, at a very high level, some basic features of a FinFET device. In this example, the FinFET device 10 includes three illustrative fins 14, a gate structure 16, a sidewall spacer 18 and a gate cap layer 20. Trenches 22 are formed in the substrate 12 to define the fins 14. A recessed layer of insulating material (not shown) is positioned between the fins 14 in the areas outside of the gate structure, i.e., in the source/drain regions of the device 10. The gate structure 16 is typically comprised of a layer of gate insulating material (not separately shown), e.g., a layer of high-k insulating material (k-value of 10 or greater) or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device 10. The fins 14 have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device 10 when it is operational. The portions of the fins 14 covered by the gate structure 16 are the channel regions of the FinFET device 10. The gate structures 16 for such FinFET devices 10 may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques. A FinFET device may have either a tri-gate or dual-gate channel region.
Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. A FinFET device may have either a tri-gate or dual-gate channel region. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to significantly reduce short channel effects. In a tri-gate FinFET device, the “channel-width” is estimated to be about two times (2×) the vertical fin-height plus the width of the top surface of the fin 14, i.e., the fin width. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current density than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior FET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
As FinFET devices have been scaled to meet ever increasing performance and size requirements, the width W of the fins 14 has become very small, e.g., 6-12 nm, and the fin pitch has also been significantly decreased, e.g., the fin pitch may be on the order of about 30-60 nm. Accordingly, accurately defining these relatively small fin structures can be challenging. One manufacturing technique that is employed in manufacturing FinFET devices is to initially form the trenches 22 in the substrate 12 to define multiple “fins” that extend across the entire substrate 12, and thereafter remove some of the fins where larger isolation structures will be formed. Using this type of manufacturing approach, better accuracy and repeatability may be achieved in forming the fins 14 to very small dimensions due to the more uniform environment in which the etching process that forms the trenches 22 is performed.
After the trenches 22 have been formed, some of the fins 14 must be removed to create room for or define the spaces where isolation regions will ultimately be formed to separate the individual FinFET devices from one another. As noted above, the fins 14 are typically formed in a regular array. Typically, two separate fin removal or “fin cut” etching processes, involving two different etching masks, are performed to remove the unwanted fins (or portions thereof). One of these fin-removal etching processes is sometimes referred to as a so-called “FC cut” process, while the other fin-removal etching process is sometimes referred to as a so-called “FH cut” process. The FC cut and the FH cut may be performed in either order, although typically the FC cut process is performed first. The FC cut process is performed to cut the fins 14 in the direction that crosses the plurality of fins 14 by removing portions of the axial length of the fins exposed by an FC cut mask (e.g., photoresist). The FC cut process essentially defines the axial length of the fins 14 that will be positioned above one or more active regions. This FC cut process is typically an anisotropic cut process. The FH cut process is performed to remove one or more of the fin segments in a direction parallel to the plurality of fins 14 by removing portions of the axial length of the fins (or sometimes the entire axial length of a fin) located outside of and exposed by an FH cut mask. The FH cut process may be either an anisotropic or isotropic etch process depending upon the particular technique employed, as discussed more fully below.
One such removal technique used for the FH cut process is typically referred to as “Fins-cut-First,” as will be described with reference to FIGS. 1B-1E. In general, in this process, the portion of the fin to be removed is not actually formed in the substrate. Rather, the patterned fin-formation etch mask 32 is modified such that the underlying substrate material where such a fin portion would otherwise be formed is removed when the fin-formation trenches are etched into the substrate. Accordingly, FIG. 1B depicts a product 30 after a patterned fin-formation hard mask layer 32, e.g., a patterned layer of silicon nitride/silicon dioxide, was formed above the substrate 34 in accordance with the desired fin pattern and pitch. In the depicted example, only a single fin will be removed, i.e., the fin 36 corresponding to the feature 32A, to make room for an isolation region. However, as will be recognized by those skilled in the art, depending upon the desired final size of the isolation region, more than one fin may be removed.
FIG. 1C depicts the product 30 after a patterned masking layer 38, e.g., a patterned layer of photoresist, was formed above the patterned fin-formation hard mask layer 32. The patterned masking layer 38 has an opening that exposes the feature 32A (for a certain axial length into and out of the drawing page) for removal.
FIG. 1D depicts the product 30 after an etching process was performed through the patterned masking layer 38 so as to remove the exposed feature 32A of the patterned fin-formation hard mask layer 32.
FIG. 1E depicts the device 30 after the patterned masking layer 38 was removed and after a fin-formation etching process was performed through the patterned fin-formation hard mask layer 32 (without the feature 32A) so as to define full-depth trenches 40 in the substrate 34 that define the desired fins 36 across the entire substrate. Due to the removal of the feature 32A, the fin-formation etching process removes the portions of the substrate 34 that would have otherwise formed a fin 36 in the area under the feature 32A. One problem with the Fins-cut-First approach is that it inevitably causes variations in fin sizes, i.e., the dimensions 36X and 36Y are different for different fins. This is especially true between fins 36 inside an array of fins and the fins at the edge of the active region that is close to the isolation region. Such variations in fin sizes may lead to unacceptable variations in device performance. Such variations in fin sizes are caused by variable etch loading effects wherein there are different etch rates that result in different etch profiles for the fins 36 due to differing patterning densities, pitch, etc. However, one benefit of the Fins-cut-First approach is that an anisotropic etching process may be performed when forming the trenches 40 since the technique involves removing substantially all of the substrate material where the undesired fin would have otherwise been formed and there is little chance of damaging laterally adjacent fin structures.
FIG. 1F depicts the product 30 after several process operations were performed. First, a layer of insulating material 42, such as silicon dioxide, was formed so as to overfill the trenches 40. Next one or more chemical mechanical polishing (CMP) processes were performed to planarize the upper surface of the insulating material 40 with the top of the fins 36 and thereby remove the patterned fin-formation hard mask 32. Thereafter, an etch-back process was performed to recess the layer of insulating material 42 between the fins 36 and thereby expose the upper portions of the fins 36, which corresponds to the final fin height of the fins 36. Next, a gate structure (not shown) for the product 30 may be formed using either gate-first or gate-last manufacturing techniques.
Another technique employed during the FH cut process is typically referred to as “Fins-cut-Last,” and it will be generally described with reference to FIGS. 1G-1L. FIG. 1G depicts the product 30 after the patterned fin-formation hard mask layer 32 was formed above the substrate 34 in accordance with the desired fin pattern and pitch. As before, in the depicted example, only a single fin will be removed, i.e., the fin 36 corresponding to the feature 32A, to make room for the isolation region.
FIG. 1H depicts the product 30 after a fin-formation etching process was performed through the patterned fin-formation hard mask layer 32 so as to define the full-depth trenches 40 in the substrate 34 that define the fins 36 across the entire substrate. Note that, in the Fins-cut-Last approach, the size of the fins is very uniform, i.e., the dimension 36A is approximately equal to the dimension 36B. This is primarily due to the fact that, in this approach, fins 36 are formed everywhere on the wafer in a substantially uniform etch environment, i.e., there is no undesirable etch loading effects to cause variations in fin sizes.
FIG. 1I depicts the product 30 after several process operations were performed. First, a layer of insulating material 44, such as silicon dioxide, was formed so as to overfill the trenches 40. Then a CMP process was performed to planarize the upper surface of the layer of insulating material 44 with the patterned fin-formation hard mask layer 32. Next, a patterned masking layer 46, e.g., a patterned layer of photoresist, was formed above the layer of insulating material 44. The patterned hard mask layer 46 has an opening that is positioned above the underlying fin 36 that is to be removed.
FIG. 1J depicts the product 30 after one or more etching processes were performed to remove the exposed portions of the layer of insulating material 44 and the exposed portion of the fin-formation hard mask layer 32, i.e., the feature 32A, thereby forming a trench 44A in the layer of insulating material 44 that exposes the fin 36 that is to be removed. Inevitably, there will be some tapering of the sidewalls of the trench 44A when it is formed. The patterned masking layer 46 remains in position above the remaining features of the patterned fin-formation hard mask 32 when the opening is formed.
FIG. 1K depicts the product 30 after an isotropic fin-removal etching process was performed to remove the exposed axial-length portion of the fin 36 which, given the isotopic nature of the fin-removal etch process, results in a small trench 48 in the substrate 34. An isotropic etching process is performed to ensure complete remove of the fin, especially the portions of the fin 36 near the bottom of the trench 48. Although not depicted in the drawings, after the trench 48 is formed, the patterned masking layer 46 will be removed and additional oxide material (not shown) will be formed in the trench 44A where the fin 36 was removed. Then a chemical mechanical polishing (CMP) process will be performed to planarize the upper surface of all of the insulating materials with the top of the patterned fin-formation hard mask 32. Thereafter, the isolation regions between devices will be masked and an etch-back process will be performed to recess the layer of insulating material 44 between the fins 36 for each device and thereby expose the upper portions of the fins 36, which corresponds to the final fin height of the fins 36.
FIG. 1L is a cross-sectional view taken where indicated in FIG. 1K, i.e., through the axial length of the fin 36 where a portion of the axial length of that fin was removed. Typically, only a portion of the entire axial length of the fin 36 will be removed as other portions of the initially formed fin 36 will serve as permanent fins 36A for other FinFET devices. One problem with the Fins-cut-Last approach is that, due to the isotropic nature of the fin removal etching process, the cut ends 50 of the permanent fins 36A that are adjacent the portion of the fin 36 that was removed are typically subjected to relatively severe undercutting, as depicted in FIG. 1L. Such fin undercutting can adversely impact the performance of the FinFET devices that are made using the permanent fins 36A.
As it relates to the formation of FinFET devices, the number of fins of a FinFET device is an important consideration. In general, a FinFET device with a greater number of fins tends to exhibit greater performance than a FinFET device with a lesser number of fins. Accordingly, all other things being equal, a FinFET device with a relatively greater number of fins would be a candidate for various high performance applications, such being included as part of a critical path for a logic circuit on an integrated circuit product. On the other hand, FinFET devices with a lesser number of fins may be more suitable for applications involving less relative power consumption, as such FinFET devices tend to exhibit relatively lower off-state leakage currents. Accordingly, such FinFET devices may be employed in non-critical path circuits where power consumption and power management is an important factor.
In general, there are two different ways that may be employed in an attempt to produce FinFET devices with different numbers of fins. Historically, FinFET devices have been formed in and above active regions that have a rectangular configuration. FIG. 1M is a simplistic depiction of one illustrative example of how different FinFET devices, each having a different number of fins, may be formed above spaced-apart active regions that have a rectangular configuration. As shown therein, the product is comprised of a plurality of fins 14, a plurality of dummy gates 52 and a plurality of active gates 54. First and second FinFET devices 56, 58 (each of which are two-fin devices) are formed in and above spaced-apart rectangular active regions 60, 62, respectively. FIG. 1M also depicts first and second FinFET devices 64, 66 (each of which are three-fin devices) formed in and above spaced-apart rectangular active regions 68, 70, respectively. Such a configuration does result in a plurality of FinFET devices 56, 58, 64 and 66 having a different number of fins. However, each of the FinFET devices are formed above spaced-apart, rectangular shaped active regions 60, 62, 68 and 70, respectively. One positive aspect of the embodiment shown in FIG. 1M is that there is little or no undercutting of the cut end surface of the fins, as described in FIGS. 1K-1L above (see surface 50 in FIG. 1L). One negative aspect of the approach depicted in FIG. 1M, is that there is a relatively significant area penalty (e.g., 10-20%) associated with forming the four spaced-apart, rectangular active regions 60, 62, 68 and 70.
FIG. 1N depicts another illustrative way wherein FinFET devices may be formed with a different number of fins. In this embodiment, so-called “tapered” FinFET devices 80, 82 are formed in and above non-rectangular shaped active regions 84, 86, respectively. At the bottom of FIG. 1N, the non-rectangular shaped active region 86 is shown by itself so as to clearly show its non-rectangular configuration when viewed from above. A FinFET device formed above a non-rectangular shaped active region (as opposed to a traditional rectangular shaped active region) may be generally referred to as a “tapered” FinFET device, in that the active region is configured or tapered (i.e., non-rectangular) so as to allow formation of FinFET devices (with different numbers of fins) above that tapered, non-rectangular shaped active region. In the depicted example, each of the tapered FinFET devices 80, 82 include a two-fin FinFET device and a three-fin FinFET device. Such tapered FinFET devices offer significant scaling benefits as compared to the traditional FinFET devices shown in FIG. 1M that are formed above the spaced-apart rectangular active regions 60, 62, 68 and 70. However, one drawback to forming tapered FinFET devices is that, when removing fins as described above, there will typically be significant undercutting of the fins due to the isotropic fin-removal etch process that is performed to remove undesired portions of the axial length of the fins during Fins-cut-Last approach that is used during the FH cut process, as described above. As noted above, such fin undercutting can tend to degrade device performance.
The present disclosure is directed to various hybrid fin cutting processes for FinFET semiconductor devices that may solve or reduce one or more of the problems identified above.